1. Field of the Invention
The present invention relates, in general, to a method for fabricating a semiconductor device and, more particularly, to a method for forming a multilayer-wiring structure in a semiconductor device.
2. Discussion of the Related Art
To achieve highly integrated semiconductor devices with high operating speed, pattern dimension of the semiconductor devices has been progressively miniaturized. In particular, in a formation process for a multilayer-wiring structure in a semiconductor device, as the width of the wiring layers becomes narrower and the distance between the layers becomes shorter, the size of contact hole needs to be finer.
Recently, a reactive ion etching (hereinafter, "RIE") process has been employed for forming a contact hole, which is poor in side etch and is superior in etch control.
Conventional methods for forming a two-layer wiring structure, including the formation of contact hole by use of the RIE, have been proposed and are discussed below.
FIGS. 1a-1d show a stepwise illustration of a conventional method for forming a multilayer wiring structure in a semiconductor device.
As shown in FIG. 1a, a thermal oxidation process is applied to a substrate 1 to form a silicon oxide film 12. Al--Si is deposited on the silicon oxide film 12 and then subjected to patterning to form a first wiring layer 13 consisting of a plurality of parallel, spaced-apart wirings. On the entire resulting structure, a nitride film 14 is formed, as an insulating film, using a plasma process.
To plane the surface of the nitride film 14, a silica solution is coated on the surface thereof, and an annealing process is applied to the silica solution to form a silica insulating film 15, as shown in FIG. 1b.
On the silica insulating film 15, as shown in FIG. 1c, a photoresist is coated, which is subsequently subjected to exposure and development using a conventional photo-etching process to form a photoresist pattern 16. Utilizing the photoresist pattern 16 as a mask, the RIE process is carried out to selectively etch the silica insulating film 15 and the nitride film 14. As a result, a contact hole 17 is formed, exposing the first wiring 13 therethrough.
After the photoresist pattern 16 is removed., as shown in FIG. 1d, Al--Si is deposited on the entirety of the silica insulating film 15, including the contact hole 17, using a conventional sputtering process and then is subjected to patterning to form a second wiring layer 18. As a result, a semiconductor device having a two-layer wiring structure is fabricated.
However, problems exist in the above-mentioned conventional method. For example, it is necessary to incline the side wall of the contact hole 17, which is formed from an interlayer insulating film consisting of the nitride film 14 and the silica insulating film 15, at angles ranging from about 45.degree. to about 55.degree. to prevent the second wiring layer 18 from shorting the contact hole 17. Taking into account the area ratio of the photoresist pattern 16 to the nitride film 14, the etching speed, and the stability of the etched state, the second wiring layer 18 formed on the side wall of the contact hole 17 of the interlayer insulating film, consisting of the nitride film 14 and the silica insulating film 15, becomes thin due to the steepness of the side wall of the contact hole 17, as shown in FIG. 1c. In such a thin portion of the second wiring layer, a short can easily occur due to high current density therein.
In addition, provided that the interlayer insulating film, consisting of the nitride film 14 and the silica insulating film 15, is thick, the variations in etching dimension becomes large due to the recession in the photoresist 16. Accordingly, it becomes difficult to make the contact hole finer.
In an effort to solve these problems, a method for forming a multilayer wiring structure has been disclosed in the Korean Patent Publication No. 90-1834 to Mase Yaskaz et al. This method is explained with reference to FIGS. 2a through 2e.
First, on a substrate 1, as shown in FIG. 2a, a silicon oxide film 2 is formed, on which an Al--Si alloy is subsequently deposited and is patterned with a photo-etching process using a photosensitive film 4 to form a first wiring layer 3.
After the photosensitive film 4 is removed, as shown in FIG. 2b, a plasma chemical vapor deposition (CVD) process is carried out many times to form thick nitride films 5 and 6 at not more than 300.degree. C., at which protrusions are not generated. A silica insulating film 7 is formed on the nitride film 6 to plane or smooth stepped parts caused by the first wiring layer 3.
Next, as shown in FIG. 2c, a photosensitive film is coated on the silica insulating film 7 and is then exposed and developed with a photo-etching process to form a photosensitive film pattern 8. Using the photosensitive film pattern 8 as a mask, the silica insulating film 7 and the nitride films 5 and 6 are etched, in that order, to form a contact hole 9 exposing the first wiring layer therethrough.
After the photosensitive film pattern 8 is removed, as shown in FIG. 2d, an annealing process is carried out at 500.degree. C. for 15 minutes to form a protrusion 10 on the first wiring layer 3 exposed in the contact hole 9. The formation of the protrusion 10 is due to a "hillock" phenomenon of Al constituting the first wiring layer.
Finally, as shown in FIG. 2e, another Al--Si alloy is deposited on the entirety of the structure resulting from FIG. 2d to form a second wiring layer 11, which contacts the first wiring layer 3 in the contact hole 9.
The method of Mase Yaskaz et al. takes advantage of the Al "hillock" phenomenon generated from annealing Al to fill the contact hole 19, leading to the connection of the lower wiring with the upper wiring.
However, since the first wiring layer is used to form the protrusion (Al "hillock"), there is generated a void caused by the motion of Al in the portion of the wiring adjacent to the protrusion 10, damaging the wiring. In addition, the size of the protrusion cannot be controlled, and hence, the method of Mase Yaskaz et al. is inferior in reproducibility and homogeneity.